Multi-Objective Genetic Algorithm-Based Technique for Achieving Low-Power VLSI Circuit Partition

Minimizing the power consumption of electronic systems is one of the most critical concerns in the design of integrated circuits for very large-scale integration (VLSI). Despite the reality that VLSI design is known for its compact size, low power, low price, excellent dependability, and high functionality, the design stage remains difficult to improve in terms of time and power. Several optimization algorithms have been designed to tackle the present issues in VLSI design. This study discusses a bi-objective optimization technique for circuit partitioning based on a genetic algorithm. The motivation for the proposed research is derived from the basic concept that, if some portions of a circuit's system are deactivated during the processor's idle time, the circuit's power consumption is automatically reduced. To reduce the overall system's power consumption, maximization of sleep time and minimization of net cuts are required. To achieve these, an effective fitness function has been constructed in such a way that the balance criteria are also maintained. The approach has been tested on a set of net lists from the ISPD'98 benchmark suite, each containing 10 to 30 nodes. The experimental results are compared with two existing methods that clearly indicate the acceptability of the suggested method. The suggested strategy achieves an average reduction of 24.69% and 31.46% for net cut, whereas average extensions of 15.20% and 12.31% are observed in sleep time when compared with two existing methods. The proposed method also achieves an average power efficiency of 14.98% and 12.09% with respect to these two state-of-the-art methods.


Introduction
VLSI chips are widely employed in today's world, possibly in almost every sector of engineering, including computers, electronics, automobiles, voice and data communication networks, and many more.Thus, VLSI physical design and automation have become rapidly increasing industries.Reduced average power consumption in integrated circuits is a significant challenge for VLSI physical design.Researchers and industries are always making their best efforts to develop improved algorithms and methodologies for improving VLSI circuit performance.If the power consumption of the circuit is low, modern electronic gadgets such as smart phones, tablets, and laptops will have a longer battery life.This will minimize the chip's heat dissipation and energy consumption automatically.In CMOS devices, dynamic and sub-threshold leakage power should be decreased.

ISSN: 0067-2904
Equation (1) can be used to measure the average dynamic power [1] of a circuit.Here, f denotes the operation's frequency, and C denotes the load capacitance, which comprises gate as well as wire capacitances.V DD is the applied supply voltage, and N denotes the number of switches.The second term of the equation shows the power dissipation owing to leakage current, abbreviated as I leak .
A verage =1/2×C×V DD 2 × N× f+I leak ×V DD 2 (1) The load capacitance (C) and switching activity (N) should be lowered to minimize dynamic and sub-threshold power.To achieve these objectives, a significant amount of effort and time was invested in developing a high-quality circuit partitioning algorithm.Partitioning is a method for dividing a complex component of the circuit into smaller components for easier and more efficient handling.Circuit partitioning is a difficult non-polynomial (NP) issue.It is more suitable to adopt some heuristic approaches or bio-inspired algorithms to improve the quality of circuit partitioning in a shorter amount of time.The first and most important purpose of these strategies should be to reduce the number of net cut sizes so that the number of partition-to-partition linkages is kept to a bare minimum.By minimizing net cuts among the circuit's partitions, the load capacitance gets reduced.Another goal of the partitioning strategies should be to maximize sleep durations while reducing switching activity.The components (or portions) are said to be in sleep mode when they exhibit no activity during a time interval.By using some control signals, power can be saved during this idle time.As a result, the whole system's power usage will be lowered.It is possible to maximize sleep time while minimizing transmission power loss [1].
Various optimization algorithms have been developed to address the existing VLSI design problems, notably in terms of optimizing the total wire length and area as traditional design factors.VLSI improvements in recent years have focused on extending design objectives and restrictions to include minimization of net cut and switching activity, too.
A genetic algorithm has higher parallelism, which means it has more parallel points.Chen et al. [2] suggest various strategies for achieving a better solution by altering the crossover point selection.Individual chromosomes were compared with the crossover operator in this procedure, and chromosomes were created based on the difference between the individual chromosomes.Yuen and Chow [3] developed an approach in which mutation operators were emphasized and the chromosomes were kept track of to minimize revisiting and lower the program's total run time.Another essential method developed by Jigang and Srikanthan [4] is efficient for hardware and software partitioning, which is concerned with improving the system's power estimation and overall running time.Gill et al. [5] suggested a genetic algorithm-based strategy for circuit partitioning, in which they discovered the average minimum and average net cut of circuits.They do, however, reveal that most previous methodologies are insufficient in terms of intelligent chromosomal selection for enhanced time.Arato et al. [6] offered a fascinating study in which partitioning is done using both integer linear programming (ILP) and genetic algorithms (GA).In this investigation, GA was found to be superior to ILP in terms of reaching system runtime.Prakash et al. [7] show a combination of Ant colony optimization and particle swarm optimization (PS-ACO) algorithms that deal with VLSI partitioning for multi-objective optimization with parameter cut net, delay, and sleep time.Another noteworthy work recently proposed by Prakash and Lal [8] was a Particle Swarm Optimization (PSO) based multi-objective VLSI circuit partitioning approach.But they employed bi-partitioning of circuits in both cases [7,8].
Chellamani and Chandramani [9] suggested an effective optimization method.To optimize energy management, they applied a Satin Bowerbird Optimization (SBO) approach and a machine learning-based algorithm.An effective Satin Bowerbird Optimization (SBO) based VLSI circuit partitioning algorithm was devised by R. P. Guru and V. Vaithianathan [10].They tested their method on the ISCAS'85 benchmark circuit, taking into account parameters like delay, area, and power.Finally, they established that their circuit partitioning method was efficient after comparing it with other methods like simulated annealing, PSO, ACO, etc.
Vinay Kumar et al. [11] reviewed 52 papers that were associated with optimization and mentioned their outcomes, including bio-inspired methods.They examined current trends in VLSI design improvements and future developments.A review of the many contributions of particle swarm optimization (PSO) and simulated annealing (SA), as well as VLSI design floor planning concerns, has been investigated.
The concept of multi-objective optimization was examined by Martins et al. [12] in the analog integrated circuit layout automation of placement procedures.They presented analog floor plan automation using simulated annealing and limited archive-based multi-objective optimization algorithms with better exploration of unworkable portions of the solution space.Funkej et al. [13] have studied optimal floor planning methods.On MCNC, there are block packing instances as well as an industrial example with hundreds of nets and 27 rectangles; they used their CONTAINMENT and SPARK algorithms for efficient floor layout.In addition, they demonstrate how to apply this approach to larger examples that cannot be addressed in a fair period of time in an optimal manner.Several well-known VLSI circuit partitioning algorithms have been widely employed to solve a variety of VLSI layout optimization issues.There are still certain power and area issues that need to be addressed to keep up with current VLSI developments.These observations motivate us for this work.The main contribution of the proposed work can be listed as follows: 1.A hyper graph is used to represent the circuit partitioning problem, allowing complicated VLSI circuit relationships (connections) to be simply described over pair-wise relationships in a conventional graph.2. Formulation of a new multi-objective fitness function that optimizes net cut and sleep time at the same time, considerably improving circuit performance, lowering system layout costs, and reducing power consumption.
In this work, a genetic algorithm-based multi-objective algorithm is introduced for k-way circuit partitioning that simultaneously optimizes sleep time and net cut.Because it separates the circuit into k-sub circuits, the suggested method is known as "k-way" (multi-way) circuit partitioning.The suggested method's performance is assessed using conventional benchmark circuits and compared to other current approaches.The proposed multi-objective algorithm's usefulness is demonstrated by the experimental findings.Definition 2: A net n is considered to be cut in a hypergraph-based circuit partitioning if it connects more than one segment of a circuit block, i.e., the net is outside of a partition or block.If all connected modules with the net are within a partition, the net is considered to be uncut.

Problem Formulation
In this work, a GA-based multi-objective algorithm is introduced for k-way circuit partitioning that simultaneously reduces net cut and maximizes sleep time.Since maximizing sleep time also decreases the circuit's power consumption, the power efficiency is also calculated for the proposed method.

Net cut minimization
When a circuit is represented as a hypergraph, it is made up of a set of interconnected modules and nets.Every net is connected with multiple modules.Assume that the hyper graph H has m number of modules T = {t 1 , t 2 , ..., t m } and n number of nets S = {s 1 , s 2, ..., s n }.The circuit is divided into K blocks using the K-way partitioning algorithm.The purpose of this partitioning technique is to reduce the total number of nets cut.x ip is set to 1 when the i-th module t i is located in the p-th partition, otherwise, x ip is set to 0. Similarly, if j-th net s j connects the modules, all of which are within p-th partition, y jp is set to 1; otherwise, y jp is 0. Thus if net s j does not provides cut, ∑ jp = 1.Hence to minimize the net cut, this summation, overall net should be maximized.This can be mathematically expressed as Equation (2).
(2) Equation ( 2) can also be expressed as equation (3).F 1 =Minimize (n -∑ ∑ jp ) (3) Due to the fact that a module can be assigned to a single partition, module placement constraints can be specified by Eqs. 4 and 5.
(4) and B avg *(1-α/100)<=B i <=B avg *(1+α/100) (5) where B i represents the area of partition i.Since in the partitioning algorithm, area of each partition should be nearly equal with slight deviation, B i should be between B avg *(1-β/100) and B avg *(1+ β /100), where B avg = (sum of areas of all modules / number of partitions) and β is the imbalance factor.This is an NP-hard problem that can be addressed using 0-1 linear integer programming [3].

Sleep Time Maximization
Recent studies [8] have demonstrated that sleep time can be maximized.As stated earlier, the hyper graph H has m number of modules T = {t 1 , t 2 , ..., t m }.As an example, if I 1 = (3, 7) and I 2 = (5, 9) then I 1 ∩I 2 = {5, 6, 7}.Again if R j = {I j1 , I j2, ..., I jY } and R i = {I i1 , I i2, ..,I iX }, then R i ∩R j = {I 1 ∩I 2 | I 1 ∈R i , I 2 ∈R j }.D(t i , t j ) is the cardinality of R i ∩R j and represents the total sleep duration between modules t i and t j .
Here, m denotes the total number of modules in the partitioning technique.Modules {t 1 , t 2 , ..., t m } are partitioned into K blocks {S 1 , S 2 ,...S k }.The sleep duration of p-th partition S p i.e.SD (S p ) can be calculated as D (t i , t j , …,t z ) where modules t i , t j , …, t z belongs to S p .Equation ( 6) can be used to maximize sleep duration in total for the circuit, where SW p denotes the number of switches in the partition S p .The amount of times a partition has to be turned off due to sleep is shown by the number of times it must be switched off over the overall time length.is a parameter that is determined by the available technology and circuitry in modules, and controls the proportionate relevance of overhead terms (SW p ) and power savings (SD(S p )) .In this experiment, is taken into account as 1.F2 = Maximize (∑ (S p ) -β∑ p ) (6)

Composite function
To achieve dual objectives, i.e., minimizing net cut and maximizing sleep time duration, the composite objective function is defined in Equation (7).F = Minimize (µ c ×F 1 +µ s ×1/(1+ F 2 )) (7) µ c and µ s denote the weights of the first and second objectives, respectively, such that µ c + µ s =1.In this proposed methodology, equal weights have been assigned to these two objectives with µ c = µ s = 0.5.

Power efficiency
Let PS 1 represent power consumption in sleep mode, and let PS 2 denote power consumption when not in sleep mode in the suggested partitioning technique.Since there are K partitions (S1, S2,..., SK), PS 1 can be estimated as .( 9)

Methodology
To produce the optimum bi-objective function given in Equation ( 7), a genetic algorithmic approach is applied.From the circuit description, two matrices are created.Net matrix N (n×m) and connectivity matrix C (m×m) are used to describe the circuit having m modules and n nets.Cij=1 in the connection matrix when the i-th module is linked to the j-th module via a net, else Cij=0.Similarly, in the Net matrix, Nij=1 if the i-th net is incident on the j-th module, else Nij=0.At first, an initial population is produced by dividing the circuit into K parts randomly.Chromosomes are used to symbolize the K-way partitions when the population is created.Then, to make new chromosomes, genetic operators such as crossover and mutation are applied to these chromosomes.To optimize the bi-objective function given in Equation (7), the fitness values of these additional chromosomes are determined.For the next generation, the best-fitting chromosomes are selected.These stages are repeated until the desired result is attained.The complete algorithm is listed below.

Proposed algorithm:
INPUTS: A circuit having n nets and m modules where m×m Connectivity matrix and n×m Net matrix, P mt Type of mutation, P m Probability of mutation, type of cross over, Probability of crossover, Total generations, Size of the Population, P activity Activity profiles of module, α Imbalance factor .

OUTPUTS:
Ideal solutions that achieve the objectives.
Step 1: Initial population: The starting population is created by slicing the circuits into K parts at random in order to satisfy the balance restrictions as described in Equation ( 5).
Step 2: Chromosome Encoding: In the beginning, the m-length chromosome E 1 E 2 ….E m encodes each solution, and E i =p when the i-th module is assigned to the p-th partition.Because K-way partitions are produced, a chromosome is a set of partition numbers ranging from 1 to K.
Step 4: The rank of each chromosome in the initial population is calculated by evaluating the fitness function µ c × F 1 + µ s × 1/(1 + F 2 )) where F1 and F2 are given by Eqs. 3 and 6, respectively, assuming µ c = µ s = 0.5.
Step 5: Use the genetic operators mutation and crossover, depending on P m , P c , P mt , and P ct, to generate a new chromosome set CS.

Step 7:
The population is updated with the chromosomes in CS whose fitness values meet the requirement.
Step 9: Repeat Step 6 to Step 9 while t ≠ G.
Step 10: Output the optimal solutions.
Step 11: Record the optimized net cut and optimized sleep time.
Step 12: Calculate the power P 2 of the optimal solution.
Step 13: Calculate the power efficiency, P efficiency of optimized partition using Equation (8) Step 14: Output power efficiency, P efficiency .

Results and Discussions
On the ISPD 98 benchmark [16], the suggested method is evaluated.MATLAB 21a is used for implementation on an Intel Core i3 (10th Gen) system that has a RAM size of 8 GB.ISPD 98 contains 997 benchmark circuits with 10 to 30 nodes and 7 to 25 nets.The experiment has been carried out for two and four-way partitioning separately.Table 1 shows ten circuits for 2-way partitioning and ten circuits for 4-way partitioning, along with the number of nodes and nets in each of these benchmarks.Initially, the benchmark circuit descriptions are represented as a hypergraph in terms of the matrix of connectivity and the matrix of nets.Following that, the hypergraph is initially partitioned into two and four blocks randomly, maintaining the balanced condition, to create the initial population.On these initial partitions, multi-objective GA is used.The proposed fitness function optimizes net cut and sleep time simultaneously.The optimal net cut, sleep duration, and power efficiency for the representative circuits are illustrated after applying the proposed methodology, which is shown in Tables 2 and 3 for two-way and four-way partitioning, respectively.The power efficiency of the optimized partition is calculated using Equation (8).
To assess the acceptability of the proposed method, the experimental result is compared to that of other existing methods.Because the majority of works in the literature use the bipartitioning method, the result of two-way partitioning is compared with two different methods proposed by Prakash and Lal [7,8].In [7], they proposed a circuit bi-partitioning method using PS-ACO, whereas in [8], only a PSO-based method is used.Comparisons are made concerning the number of net cuts, sleep time, and power efficiency and are given in Table 4.It can be observed from Table 4 that the numbers of net cuts are decreasing and sleep times, as well as power efficiencies, are increasing for most of the representative circuits.The average number of net cuts, sleep time, and power efficiency are also calculated for these ten representative benchmarks.The average net cuts are decreased by 24.69% and 31.46%,average sleep times are increased by 15.20% and 12.31%, and power efficiency is achieved at 14.98% and 12.09% with respect to [7] and [8].

Conclusions
A dual-objective evolutionary algorithm has been suggested for K-way circuit partitioning that maximizes sleep time while minimizing net cut size.The circuit partitioning problem is NP-hard.The initial population is created by arbitrarily partitioning a circuit in Kways such that the balanced condition is met.Each chromosome is coded appropriately, and crossover and mutation operators are used to produce new solutions.To create a high-quality solution, the likelihood of crossing and mutation has been kept low.The GA can easily encode the design variable into bits because it is discrete by nature.For example, in 2-way partitioning, it is easy to encode the design variable from 1 to 2. The suggested method is used to improve circuit partitioning using the ISPD'98 benchmark suite.From the experimental results, it can be observed that the suggested technique improves the quality of the results significantly.The results are compared with two existing methods.The average improvement of net cut and sleep time is 24.69% and 15.20%, respectively, when compared with [7], whereas it is 31.46%and 12.31% when compared with [8].Since the proposed method maximizes sleep time, the system's power usage has been reduced.The proposed method also achieves power efficiencies of 14.98% and 12.09% with respect to [7] and [8].The proposed strategy will aid in achieving faster convergence without sacrificing solution quality.

Figure 1 :
Figure 1: Hyper graph with 8 modules and 4 nets which is partitioned into 4 blocks.
2. PreliminariesDefinition 1: A hypergraph G = (M, Z) has a collection of vertices M which is called modules, and a collection of nets Z which is called hyper edges, among the modules.If a net n ∈ Z connects a set of modules v ∈ M, then net n is defined by the set of vertices v.The set of vertices of a net n are referred to as its pins.The size of a net is determined by the number of pins in it.
If i-th module t i is in an idle state within the specified time frame (b, e), it is possible to put the module to sleep, where b and e denote the start and end of the time span, respectively.Two time periods (b 1 , e 1 ) and (b 2 , e 2 ) are said to be non-overlapping if b 1 >=e 2 or b 2 >=e 1 .Assume that R i indicates a set of non-overlapping intervals for t i .During this time, it's possible to put the i-th module to sleep.R represents the entire idle sets of all modules within the circuit, i.e.R = {R 1 , R 2 ,..., R m }.The time interval for a module may be empty, which indicates that the module has no idle time.If b 1 ≤ b 2 ≤ e 2 ≤ e 1 , it is assumed that the first interval covers the second.If I 1 and I 2 indicate two time intervals, then I 1 ∩I 2 is the collection of time units that both I 1 and I 2 have in common.

Table 1 :
Representative circuits with number of nodes and number of nets.